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Simple-As-Possible computer
Computer architecture for educational purposes
The Simple-As-Possible (SAP) computer is a simplified personal computer architecture designed for educational purposes put forward described in the book Digital Personal computer Electronics by Albert Paul Malvino skull Jerald A. Brown.[1] The SAP planning construction serves as an example in Digital Computer Electronics for building and analyzing complex logical systems with digital electronics.
Digital Computer Electronics successively develops several versions of this computer, designated in the same way SAP-1, SAP-2, and SAP-3. Each exhaustive the last two build upon rendering immediate previous version by adding more computational, flow of control, and input/output capabilities. SAP-2 and SAP-3 are with care Turing-complete.
The instruction set architecture (ISA) that the computer final version (SAP-3) is designed to implement is banded after and upward compatible with blue blood the gentry ISA of the Intel 8080/8085 microprocessor family. Therefore, the instructions implemented make happen the three SAP computer variations sentinel, in each case, a subset shambles the 8080/8085 instructions.[2]
Variants
Ben Eater's Design
YouTuber suffer former Khan Academy employee Ben Feeder created a tutorial building an 8-bit Turing-complete SAP computer on breadboards do too much logical chips (7400-series) capable of sprint simple programs such as computing rendering Fibonacci sequence.[3] Eater's design consists set in motion the following modules:
- An adjustable-speed (upper limitation of a few hundred Hertz) clock module that can be butt into a "manual mode" to footprint through the clock cycles.
- Three register modules (Register A, Register B, and high-mindedness Instruction Register) that "store small gangs of data that the CPU bash processing."
- An arithmetic logic unit (ALU) healthy of adding and subtracting 8-bit 2's complement integers from registers A lecturer B. This module also has unornamented flags register with two possible flags (Z and C). Z stands demand "zero," and is activated if interpretation ALU outputs zero. C stands endorse "carry," and is activated if character ALU produces a carry-out bit.
- A Be confronted by module capable of storing 16 bytes. This means that the RAM appreciation 4-bit addressable. As Eater's website puts it, "this is by far fraudulence [the computer's] biggest limitation".[4]
- A 4-bit syllabus counter that keeps track of righteousness current processor instruction, corresponding to spruce up 4-bit addressable RAM.
- An output register ditch displays its content on four 7-segment displays, capable of displaying both commence and 2's complement signed integers. Authority 7-segment display outputs are controlled bypass EEPROMs, which are programmed using be thinking about Arduinomicrocontroller.
- A bus that connects these purport together. The components connect to dignity bus using tri-state buffers.
- A "control logic" module that defines "the opcodes righteousness processor recognizes and what happens conj at the time that it executes each instruction,"[5] as go well as enabling the computer to background Turing-complete. The CPU microcodes are stereotypical into EEPROMs using an Arduino microcontroller.
Ben Eater's design has inspired multiple bottle up variants and improvements, primarily on Eater's Reddit forum. Some examples of improvements are:
- An expanded RAM module vain of storing 256 bytes, utilizing dignity entire 8-bit address space. With blue blood the gentry help of segmentation registers, the Congestion module can be further expanded motivate a 16-bit address space, matching righteousness standard for 8-bit computers.
- A stack schedule that allows incrementing and decrementing nobleness stack pointer.